Resistive RAM for Space Applications & the Impact of Scaling Access Circuitry

Abstract

Resistive random access memories (RRAM) have gained interest in recent years as a contender for the future of nonvolatile memory (NVM) due to their ease of integration into the CMOS process, for their scaling potential, the possibilities of which have yet to be fully realized, and for their robust radiation tolerance. To be used as a viable memory, RRAMs require a significant amount of additional CMOS-based circuitry. Recent work reported shows that single event effects in peripheral circuitry, in fact, dominate the single event response of a commercial RRAM embedded memory. However, the bulk of the work published on radiation effects in RRAM has focused on the response of the resistive element alone, particularly for TID and DD studies. This work considers the implication of the presence of access circuitry on TID and DD tolerance and the impact of variability on the efficacy of error rate predictions. Not accounting for variability in energy deposition results in drastic discrepancies for error rate predictions (nearly an order of magnitude) and will become increasingly important for highly scaled CMOS circuitry and subsequently the reliability of RRAMs. Despite the presence of an unhardened access transistor, RRAM memory cells were observed to be robust against TID and DD up to large total exposures. Radiation-induced degradation in the access transistor is likely to be a limiting factor for TID and DD effects, despite the highly robust RRAM memory element.