Improved bufferless routing via balanced pipeline stages

Abstract

Network-on-chip (NoC) architectures with emerging interconnect technologies have been developed to meet the demand for high-performance computational systems while maintaining energy efficiency. The introduction of deflection routing and bufferless router architectures offers smaller area and lower power consumption for on-chip networks that connect cache to multicore processors. The design of the deflection-routing algorithm is the key for maintaining the performance of the network. This paper presents an investigation of the hardware implementation for a bufferless router. We determine the critical path to maximize the work done per stage for a pipelined architecture. Our design improves the deflection rate when compared to previous literature. We also improve the design based upon the physical implementation by balancing the delay through the pipeline stages. Our design was prototyped using a field-programmable gate array (FPGA) to construct a mesh topology to evaluate the performance. The average latency for flits is reduced by up to 16.2% versus a baseline design.