| dc.description.abstract | Charge-trap transistors (CTTs) are commercial CMOS process transistors that employ their high-k-metal-gate dielectric layers to store charge in the gate oxide for use as embedded non-volatile memories (NVM). The low power consumption of CTTs has led to their proposed use as either digital or analog memories within neuromorphic architectures. However, a total-ionizing-dose (TID) environment can similarly introduce trapped charges within dielectric materials potentially introducing a competing memory effect.
This dissertation reports how TID affects DC characteristics of individual CTTs in two process technologies (GF 22FDX and 14LPP) and evaluates the implications for CTTs used as nonvolatile memories. It is demonstrated that charge-trap transistors can maintain their programmed state in TID environments when not degraded by the process isolation structures.
The key contributions of this dissertation are as follows. One, the TID response of individual 22 nm planar fully-depleted silicon-on-insulator (FDSOI) and 14 nm bulk FinFET CTTs are presented for unprogrammed transistors. In addition, the TID response is shown for CTTs programmed before irradiation as well as for transistors programmed after irradiation. Finally, the collected experimental data is then applied in a forward-looking view to simulate the potential ramifications of using CTTs as memory elements in neural networks within TID-environments.
Several important results are found. The tolerance of CTTs to TID is found to depend primarily on the properties of the nearby insulators, not on the memory element. 22 nm FDSOI CTTs lose their programmed state above ~150 krad(SiO2) due to hole trapping in the buried oxide while 14 nm bulk FinFETs are minimally affected by TID. Programming is also shown to result in sufficient electron trapping in the gate to support non-volatile memory applications for both technologies. Finally, application of the experimental data to explore preliminary neural network simulations demonstrates that classification accuracy depends on the architecture, not just the process technology, and classification accuracy gradually decreases with increasing TID. | |
