Bias and Threshold-Voltage Dependencies of Single-Event Upsets in a 7-Nm Bulk FinFET Technology

Abstract

In this work, single-event upset responses of D flip-flop designs with different threshold-voltage options in a 7-nm bulk FinFET technology are examined. Experimental data imply that single-event cross-section depends heavily upon supply voltage and particle linear energy transfer (LET) values. For close-to-nominal supply voltages and low-LET particles, the single-event upset response differs very little between threshold-voltage options; however, for low supply voltages and high-LET particles, experimental data indicates that flip-flops are more susceptible to single-event upsets at higher threshold voltages. These results are consistent with schematic-level simulations run to estimate the effect of threshold voltage on single-event transient (SET) pulse width and D flip-flop feedback-loop delay. Additional Technology Computer Aided Design (TCAD) simulations show that SET pulsewidths for worst-case strikes on an inverter are largely independent of threshold voltage. All these results together suggest that the weak dependence of single-event upset response on threshold voltage is due to the structure of FinFETs and the related charge-collection mechanisms.