SE Response of Guard-Gate FF in 16-nm and 7-nm Bulk FinFET Technologies

Abstract

With scaling of CMOS technology, single event effect (SEE) has become more and more significant due to the increasing packing density and the reducing supply voltage and node capacitance. Therefore, radiation hardened by design (RHBD) technology become even important for design engineers working at advanced technology nodes. In this work, a Guard-Gate Flip-Flop (GG-FF) design with improved single event reliability (SER) has been investigated. Design was implemented with conventional D-FF in 16-nm and 7-nm bulk FinFET technologies. Tests were carried out with alpha particles, neutrons and heavy ions with different supply voltages, operating frequencies and linear energy transfer (LET) of particle. The GG-FF design did not show any upset with alpha particles at nominal supply voltage for both technology nodes. The SE performance of GG-FF show improved performance compared to D-FF at both 550 mV and 750 mV for 7-nm node with fast neutron. Heavy-ion test results show that even at high operating frequency, the SER of Guard-Gate (GG) design is more excellent than conventional D-FF design. The heavy-ion test results have also been used to evaluate the single-event transient (SET) pulse with distribution at different technology nodes.