Single-Event Effect Mitigation in Pipelined Analog-to-Digital Converters

Abstract

Analog-to-digital converters (ADCs) are necessary circuits in many space, military, and medical circuit applications. Intelligence, surveillance, reconnaissance, and communication missions all require high performance ADCs. Speed, resolution, and power are concerns in high performance designs. Unlike commercial applications, space, military, and some medical electronics must also be able to function in a radiation environment. This additional complexity provides an interesting and needed area of research.

The goal of this work is to understand single event effects (SEEs) in high-speed ADCs, so the impact of design topologies and mitigation techniques can be evaluated for Department of Defense (DOD) or commercial space deployment. This goal is broken into two parts. The first part characterizes and explains the single event effect response, and presents a novel method of evaluating SEEs in ADCs through the use of frequency domain analysis. The second part provides additional circuit design alternatives for hardening pipelined ADCs: the use of comparator triple modular redundancy or robust encoder logic in the front pipeline stages, dual-path hardening in switched-capacitor sub-circuits, and applying analog layout techniques to all transistors-pairs along the fully-differential signal path. The conclusion of this work helps designers achieve ADCs for the next generation applications, influence experimental testing methodologies, and applies to other high-speed mixed signal applications.