Soft-error mitigation at the architecture-level using Berger codes for error detection

Abstract

Soft-error mitigation using design techniques at the architecture-level can overcome the limitations of process and circuit-level mitigation techniques in advanced technologies. This thesis presents two architecture-level error detection and correction strategies that target the Arithmetic Logic Units (ALU) within a microprocessor. The ALU was chosen because it is the heart of a microprocessor and the errors that affect it are unlike those that affect the rest of the microprocessor. The error detection code used for encoding the data is Berger code. A Register-Transfer Level (RTL) model of the circuits was built using VHDL code and then simulated. The designs were then synthesized using the FreePDK library for area, speed, and power calculations. The merits and simulation results of the two implementations are discussed. Both strategies show an effective means to detect and recover from radiation-induced soft errors; however, the area cost and speed penalties of these strategies are too severe for practical use.