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Upset trends in flip-flop designs at deep submicron technologies

dc.creatorBenakanakere Sheshadri, Vijay
dc.description.abstractAdvances in fabrication technologies for semiconductor integrated circuits (ICs) have resulted in sub-100 nm feature sizes. Along with this desired reduction in dimension has come an undesired increase in vulnerability of flip-flops to soft errors, which are caused by energetic particles that either directly or indirectly deposit energy, and create electron-hole pairs in the semiconductor material. These charges, when collected at a circuit node, perturb the associated node voltage, creating a transient pulse, which may alter the data stored in the flip-flop, causing a single- event upset (SEU). Decreasing technology feature size has resulted in higher packing densities, as a result of which, single-event related charge might be collected at multiple nodes in a circuit. Circuit-level simulations predict increased vulnerability of flip-flop designs and increased occurrence of single-event upsets in advanced technologies due to multi-node charge collection from single-ion strikes. This trend is examined by simulating 3D models of the flip-flops in a terrestrial neutron environment using Monte-Carlo Radiative Energy Deposition (MRED) simulations for charge deposition in several technology generations.
dc.subjectCritical Charge
dc.subjectCharge threshold plot
dc.titleUpset trends in flip-flop designs at deep submicron technologies
dc.contributor.committeeMemberDr. Robert A Reed
dc.contributor.committeeMemberDr. Bharat L Bhuva
dc.type.materialtext Engineering University

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