Mitigation Of Soft Errors In ASIC-Based and FPGA-Based Logic Circuits
With ever decreasing device feature sizes, subsequent generations of semiconductor logic circuits are more vulnerable to ionizing radiation effects when compared to their predecessors. Single Event Upsets (SEUs) and Single Event Transients (SETs) induced in Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) are a major concern for designers. In an ASIC, a single event strike can corrupt the data being processed, whereas in a FPGA, a single event strike can induce both data and functionality errors. Traditional radiation hardening techniques for ASICs and FPGAs aim to harden the circuit as a whole. Techniques like Triple Mode Redundancy (TMR), temporal redundancy, scrubbing, and reconfiguration involve significant penalties (sometimes greater than 3X). In commercial and non-critical applications, a 3X penalty cannot be tolerated. Further, most of the commercial and non-critical applications may not require a fully hardened implementation. In this thesis alternative soft error mitigation techniques are presented which improve reliability while minimizing penalties in area and performance. Part I of the thesis deals with soft error mitigation in ASICs. A two-level (VHDL and SPICE) simulation methodology is used to identify sensitive cells in a 4-bit Arithmetic and Logic Unit (ALU). A selective hardening approach is used to harden the ALU by targeting only the most sensitive cells. Trade-offs between reliability and area penalty are presented. Part II of the thesis discusses soft error mitigation in FPGAs. A 16-bit single instruction issue processor is designed with Error Detection and Correction (EDAC). Two different error detection codes (Berger Check Prediction and Remainder and Parity Check) are compared against TMR. Area and performance results of the EDAC techniques are presented.