Error Estimation and Error Reduction with Input-Vector Profiling for Timing Speculation in Digital Circuits
Timing analysis and timing closure are critical for digital circuit design. Traditional designs based on the worst-case delay to set timing constraints. However, a circuit could have dramatically different internal activity due to variations of the input workload. The critical path may not be active at all with typical input workloads. The conservative design style has limited the performance improvement potential. Better-Than-Worst-Case design aims to increase performance using timing speculation by operating the circuit with a faster clock frequency based on the typical case, while including error detection and correction to handle the timing errors that occur at the extreme cases. This dissertation presents a universal design flow to enable timing speculation for digital circuits. A new method was implemented to: (1) Obtain the dynamic settling behavior of circuit paths with the given input workload for error estimation, (2) Off-line error checking method, and (3) Activity aware dual-Vt re- synthesis error reduction method. This strategy is evaluated for its effectiveness to reduce timing errors on ISCAS 85 benchmark suite with Synopsys 32nm standard cell library. The entire design flow based on Synopsys EDA design tools and customized analysis scripts.