Design of soft-error-aware sequential circuits with power and speed optimization

Abstract

A single-event effect (SEE) of circuits is strongly dependent on the supply voltage and the physical capacitance. Reduction in supply voltage as well as technology scaling trends (smaller nodal capacitances) may result in dramatically increased sensitivity of the circuits to radiation. For this reason, SEE are especially considered challenges for low-power and high performance circuits. Hence, it is imperative to consider the SEE induced errors of the low power and high performance design when designing circuits for applications requiring high reliability. In this proposed research, a methodology to bridge the gap between experimental results and predictive models for SEE performance of sequential logic circuits have been developed. A study of the relationship between circuit SEE tolerance and power consumption is performed using this methodology. The purpose is to build a framework of designing soft-error-aware sequential circuits with power and speed optimization. A figure-of-merit (FOM) is provided for designers to make informed decisions on meeting power, speed, and SE specifications after the proposed framework. To comprehensively comment on the design parameters of different sequential logic circuits, a FOM is defined as the inverse of the product of power and SE cross-section (PCSP-1). Since minimization of power and SE cross-section is desirable, a lower PCSP value and thus a higher FOM value can be considered to be an indicator of an optimized design. This work focuses on the study of both power consumption and SEE tolerance at device and circuit-level. Sequential circuits are used as circuit examples in this proposed research. The ultimate goal of the work is to provide designers with capabilities and FOM to choose the suitable low power and SEE tolerance design for different targeted design specifications and operating environment.