Single event effects in commercial microprocessors using dynamic circuitry
In this work the impact of technology trends on alpha particle induced soft error rates in state-of-the-art commercial microprocessors has been investigated. At the device level, both critical charge and charge collection efficiency decreases as technologies move to the next generation. For the two technology nodes studied in this work, process improvements outpace the reduction of supply voltage and capacitance. At the circuit level, latch design has a profound impact on the SER contribution from the core logic part of the microprocessor. Elimination of floating nodes is the key to improving the SER susceptibility of the chip. At the system level, the contribution from the cache dominates the overall chip level SER. However, with ECC protection the SER contribution from the core logic is becoming more important to chip level SER. The SER frequency trend is determined by its circuit topology. SER contribution from the core logic decreases with clock frequency when transmission-gate latches are heavily used, and an opposite frequency trend is observed when differential sense amplifier latches are used.