Single-Event Upset Technology Scaling Trends of Unhardened and Hardened Flip-Flops in Bulk CMOS

Abstract

Alpha, heavy-ion, neutron, and proton experimental results from 130-nm to 28-nm technology nodes are establish single-event upset cross section trends in soft and hardened flip-flop designs. Trends show that at any LET value soft flip-flops show a decreasing single-event upset cross section with decreasing feature size. Hardened redundant storage node flip-flops show similar cross sections across technologies if the redundant storage node transistor spacing is held constant. Technology computer aided design (TCAD) simulations are used to show there are many competing mechanisms that influence flip-flip single-event upset cross sections as technology feature sizes decrease.