Characterization, Analysis, and Mitigation of Process, Voltage, and Temperature (PVT) Variations on Electrical Masking and Radiation-Induced Transients

Abstract

Technology scaling has increased the density of logic gates impacted by particle strikes, which affects the reliability of digital designs. Also, the impact of process, voltage, and temperature (PVT) variation enhances even low-threat transient pulses caused by particle strikes. The combined impact intensifies the propagation of radiation-induced transient pulses toward the storage elements of the design.

With advanced fabrication technologies used in the development of integrated circuits (ICs), a strategy is needed to mitigate the combined impact of PVT variations and radiation-induced transient pulses that affects the reliability of ICs. However, mitigation comes with an overhead penalty. The research analyzed a fault-tolerant design approach using a front-end flow of RTL2GDSII to mitigate the combined impact of radiation-induced transient pulses and PVT variations. The approach focuses on reducing performance-related overhead to improve reliability by characterizing a data-driven mitigation strategy and assessing a cost-to-reliability trade-off for several benchmark logic designs.

Experimental data were used to validate the technology models used for implementing the data-driven mitigation strategy.