Single-Event Characterization and Mitigation in High-Speed CMOS Communications Devices

Abstract

High-speed communication systems employ a mix of signal types and circuit topologies in order to optimize efficient data propagation. Typical serializer-deserializer (SerDes) circuits include three major sections, the transmitter, receiver, and lane. The propagating data is controlled by two global signals: bias and clock circuitry. The interfaces between the global signals and between signal domains expose the device to potential single-event (SE) vulnerability. The interfaces cannot be eliminated without sacrificing circuit performance. Traditional and recently developed analog radiation-hardening-by-design (RHBD) techniques are applied to the SE vulnerable interfaces as well as current mode logic (CML) and bias circuits in order to develop guidelines for future SE hardened designs that maximize circuit hardening and minimize power, speed, and area penalties.