dc.creator | Mahatme, Nihaar Nilesh | |
dc.date.accessioned | 2020-08-23T16:14:55Z | |
dc.date.available | 2011-12-06 | |
dc.date.issued | 2011-12-06 | |
dc.identifier.uri | https://etd.library.vanderbilt.edu/etd-12062011-113559 | |
dc.identifier.uri | http://hdl.handle.net/1803/15175 | |
dc.description.abstract | Single Event Effects (SEE) in combinational logic circuits, caused due radiation particle strikes are a major concern for modern high-speed devices. The frequency dependence of SEE in state-of-the-art 40 nm circuits is evaluated and the contribution of logic errors to the chip-level Soft Error Rate (SER) is quantified experimentally. A model is developed to help predict the frequency threshold at which logic errors could dominate the chip-level SER. Results suggest that, due to higher transistor density and higher operating frequencies, logic soft errors could exceed the flip-flop error rate for future technologies. A low overhead probabilistic technique to harden logic circuits against radiation induced errors is also developed. | |
dc.format.mimetype | application/pdf | |
dc.subject | combinational logic circuits | |
dc.subject | high speed circuits | |
dc.subject | radiation effects | |
dc.subject | single event effects | |
dc.subject | soft errors | |
dc.title | Comparison of combinational and sequential error rates and a low overhead technique for single event transient mitigation | |
dc.type | thesis | |
dc.contributor.committeeMember | Lloyd Massengill | |
dc.type.material | text | |
thesis.degree.name | MS | |
thesis.degree.level | thesis | |
thesis.degree.discipline | Electrical Engineering | |
thesis.degree.grantor | Vanderbilt University | |
local.embargo.terms | 2011-12-06 | |
local.embargo.lift | 2011-12-06 | |
dc.contributor.committeeChair | Bharat Bhuva | |