Mitigation of Radiation-induced Soft Errors Using Temporal Embedded Signature Monitoring

Abstract

Soft errors can alter the correct execution of code within a microprocessor, particularly if control logic is compromised. This thesis addresses the vulnerability of a microprocessor’s control logic by assigning a signature to each instruction; this signature is based upon the expected length of time it takes for the instruction to retire. This information is then compared to the actual retirement time and generates an error signal when a mismatch occurs. A VHDL description of a MIPS R2000 processor has been modified to test this concept. The processor was implemented in a Field Programmable Gate Array (FPGA) for fault injection and simulation using the Dhrystone benchmark. In addition, it was synthesized with the Oklahoma State University FreePDK 45 nm System on Chip Library for timing and area comparative analysis. The results showed that our proposed design reduces the control logic's vulnerability to soft errors by more than 80% while adding less than 1% overhead.