dc.creator | Pagey, Manish Prabhakar | |
dc.date.accessioned | 2020-08-23T16:05:29Z | |
dc.date.available | 2004-12-09 | |
dc.date.issued | 2003-12-09 | |
dc.identifier.uri | https://etd.library.vanderbilt.edu/etd-12032003-100902 | |
dc.identifier.uri | http://hdl.handle.net/1803/15050 | |
dc.description.abstract | Hot-carrier-induced degradation is a significant reliability concern
in aggressively scaled metal-oxide-semiconductor~(MOS) transistors.
The physical mechanisms responsible for hot-carrier degradation have
been studied over the past several decades in order to devise methods
to mitigate their detrimental effects. Several empirical and
semi-empirical models have been popularly used in the industry to
estimate the hot-carrier lifetimes of devices produced using specific
semiconductor technologies. However, such methods use several
simplifying assumptions that are not applicable to ultra-small
geometry MOS devices. Furthermore, such models are not capable of
predicting hot-carrier reliability variation with technology
modifications. Such capabilities are essential for optimizing a
technology to meet performance as well as reliability goals. In this
dissertation, we have developed a hot-carrier modeling approach that
avoids the assumptions made by traditional hot-carrier modeling
techniques. Physical models for mechanisms that are significant in
aggressively scaled device geometries have been included. In
particular, models for carrier transport and heating in the
semiconductor and injection into the insulator layers have been
carefully selected for application to short-channel devices. A
comprehensive model for the transport of injected carriers in the
oxide and their interactions with defects in the oxide and at the
oxide-semiconductor interface has been developed. The effects of
long-term carrier trapping and interface trap generation due to
hot-carrier injection have been simulated using this approach in a set
of commercial and non-commercial technologies. The framework presented
here represents an essential component of the technological design
process for assuring hot-carrier reliability in current and future
technologies. | |
dc.format.mimetype | application/pdf | |
dc.subject | modeling | |
dc.subject | semiconductor | |
dc.subject | reliability | |
dc.subject | hot-carrier | |
dc.title | Hot-Carrier Reliability Simulation in Aggressively Scaled MOS Transistors | |
dc.type | dissertation | |
dc.contributor.committeeMember | Dr. Robert A. Weller | |
dc.contributor.committeeMember | Dr. Sokrates T. Pantelides | |
dc.contributor.committeeMember | Dr. Lloyd W. Massengill | |
dc.type.material | text | |
thesis.degree.name | PHD | |
thesis.degree.level | dissertation | |
thesis.degree.discipline | Electrical Engineering | |
thesis.degree.grantor | Vanderbilt University | |
local.embargo.terms | 2004-12-09 | |
local.embargo.lift | 2004-12-09 | |
dc.contributor.committeeChair | Dr. Ronald D. Schrimpf | |
dc.contributor.committeeChair | Dr. Kenneth F. Galloway | |