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Detection of Malicious Hardware in ASICs and FPGAs

dc.creatorReece, Trey
dc.date.accessioned2020-08-23T16:02:46Z
dc.date.available2011-12-10
dc.date.issued2009-12-10
dc.identifier.urihttps://etd.library.vanderbilt.edu/etd-12022009-131433
dc.identifier.urihttp://hdl.handle.net/1803/15004
dc.description.abstractDetecting malicious modifications to a circuit is a daunting task, regardless of the medium. In a fabricated circuit, most methods of detecting hardware Trojans rely on small changes in side-channel measurements, which can easily be disturbed by the presence of severe process variation. In a Field Programmable Gate Array (FPGA), the reprogrammability and design transparency reduces the initial difficulty of inserting a Trojan to a circuit. This thesis suggests solutions for both situations. The first method uses a signature generated from altering the supply voltage to the circuit in a controlled manner; this process leads to a change in shape of the transient current response of the integrated circuit (IC). Simulation results presented show significant differences between circuits with and without malicious hardware (i.e., Trojans), despite large variations in individual transistor parameters. Second is a Trojan-protection by design method where a controllable ring-oscillator is inserted into a circuit in order to detect modifications that change the timing of its component gates. This design was able to win 2nd place in a competition held by the Polytechnic Institute of New York University.
dc.format.mimetypeapplication/pdf
dc.subjectMalicious Hardware
dc.subjectProcess variation
dc.subjecthardware trojan
dc.titleDetection of Malicious Hardware in ASICs and FPGAs
dc.typethesis
dc.contributor.committeeMemberWilliam H. Robinson
dc.contributor.committeeMemberBharat L. Bhuva
dc.type.materialtext
thesis.degree.nameMS
thesis.degree.levelthesis
thesis.degree.disciplineElectrical Engineering
thesis.degree.grantorVanderbilt University
local.embargo.terms2011-12-10
local.embargo.lift2011-12-10


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