Measurement and analysis of single event induced crosstalk in nanoscale cmos technologies

Abstract

The constant race for increasing the chip density in semiconductor integrated circuits has not only decreased the minimum device feature size but also the minimum amount of charge required to represent a HIGH node voltage. In the radiation domain, this translates into reduced charge requirements for generating a Single-Event Transient (SET) and the resulting Single-Event Upset (SEU). Most of the hardening techniques to combat these effects have focused on the propagation of SET pulses through logic gates, without regard to interconnects between them.

In these nanoscale technologies, scaling and closely packed interconnects magnify crosstalk effects causing a SET pulse to affect multiple logic paths instead of the single hit path. Such events increase the vulnerable area and the SET susceptibility of complementary metal-oxide-semiconductor (CMOS) circuits. This research analyses factors affecting the crosstalk pulse due to a SE in digital logic circuits for sub-100 nm technologies.

Specifically, the threefold objective of this research has been achieved: (i) the factors that exacerbate SE induced coupling identified using simulations and modeling (ii) a sample circuit designed, fabricated and tested to provide the first ever experimental measurement of SE induced interconnect crosstalk; and (iii) design margins and mitigation techniques to contain this effect provided. Simulation and Laser absorption experimental results obtained substantiate that the effects of Single Event (SE) induced crosstalk depend greatly on (i) the dV/dt of the aggressor pulse voltage, (ii) the interconnect length (coupling capacitance) and (iii) the driving strengths of devices connected to the aggressor and victim lines. This work has presented to the radiation effects community a new phenomenon that is gaining significance with scaling technologies and the use of commercial foundries to fabricate parts for space. As the semiconductor industry keeps up with the scaling trend of increased chip density and interconnect routing complexity, SE induced crosstalk effects are inevitable. Judicious design and layout planning using analyses performed in this dissertation can help mitigate or contain this effect.