| dc.description.abstract | Hardware-in-the-loop (HIL) simulation is an effective technique for testing an embedded system. An HIL simulation includes a plant model run in a real-time simulator, a controller run in the embedded system under test, and an interface used for communication between the simulator and the embedded system. The simulation and interfaces parts influence the HIL simulation's reliability and accuracy. Using a network as the HIL simulation's interface introduces problems like network delay and packet loss. Moreover the clocks in the simulator and the embedded system may not be synchronized. In this thesis, we include an assumption of latency in HIL simulation. By building in a latency model and comparing simulation results with actual measurement results, we were able to verify the latency assumption. From an analysis of the results, we found queuing delay to be responsible for the simulator's latency most of the time. By evaluating performance via software-in-the-loop (SIL) simulation, in which both plant and controller are run in simulation, we were able to estimate the latency's effect on SIL simulation. Through comparison of HIL and SIL simulation results, we verified that latency has the most significant influence on control performance. | |
