Characterization of Heavy-Ion Induced Single Event Transients in 32nm and 45nm Silicon-on-Insulator Technologies

Abstract

Single event transients (SET) have become increasingly important to characterize since operating frequencies have surpassed 100 MHz. A common way to characterize SETs for a specific technology is to measure the range of SET pulse widths that are generated from the heavy-ion irradiation of a chain of inverters. Often, testing is performed on only a few varieties of inverters that are available within a single technology. This thesis focuses on how the choice of standard process design kit (PDK) parameters and layout techniques affect the range of pulse widths obtained from heavy-ion irradiation of inverter chains in 32nm and 45nm partially-depleted silicon-on-insulator technology. Inverters designed with varying threshold voltage, oxide thickness, drive strength and geometry were tested along with inverters with and without body contacts. SET pulse widths are fundamentally controlled by two factors, namely, the amount of charge collection and the charge dissipation rate. Pulse width data collected from this work suggests that the charge collection is dominated by bipolar amplification, and the charge dissipation rate is dominated by the restoring current of the unstruck transistor in the inverter. Thus, the effect that various design parameters have on the inverter SET response can be understood by knowing how each design variation affects either the bipolar amplification or the inverter drive strength.