Charge Collection Mechanisms in Silicon Devices During High-Level Carrier Generation Events

Abstract

When ionizing radiation interacts with a semiconductor device, the resulting generation and collection of excess charge carriers can result in a brief transient current at the device terminals. These transient current pulses can negatively impact device and circuit operation, which poses a critical reliability concern for systems where continued, reliable operation is tantamount to success.

A thorough understanding of charge collection mechanisms provides device and circuit designers with the tools to make well-informed decisions about the designs of microelectronic components intended for spaceflight applications and other harsh radiation environments.

In this work, charge collection mechanisms following high-level carrier generation conditions (which could be caused by many heavy ions in the space radiation environment) are investigated using experimental measurements, device-level numerical simulations, and recent theoretical developments. Broadbeam heavy-ion irradiation and backside two-photon absorption laser exposure on several bulk-silicon test structures is used to emphasize the significance of depletion region potential modulation on the overall device response. The device response is measured using high-speed transient capture methods, and, when needed, device-level simulations are used as a means to explain the overall device response.

Key findings reveal that significant modulation of the device depletion region can lead to the saturation of current transient peaks, highly efficient charge-collection processes, and, in cases where multiple junctions are in close proximity, the recovery of the struck junction may lead to a simultaneous response at a nearby junction.

These discussions are primarily focused on the response of a reverse-biased n-well over p-substrate diode, which are commonly found in many semiconductor devices. However, because devices and circuits typically rely on the interaction of multiple semiconductor junctions, the effects of n-well potential modulation on the device-response of a PMOSFET following a high-level carrier generation event is also investigated through both experimental measurements and device-level simulations. Where applicable, these insights are used to inform the development of predictive analytical models for the peak transient current and total collected charge following a high-level carrier generation event.