Layout-Based Fault Injection for Combinational Logic in Nanometer Technologies

Abstract

As feature sizes and operating voltages decrease, single-event transients from particle strikes in logic circuits become more probable. Much literature is available on the effects of these events in memory, but with increasing clock speeds, combinational logic has also been shown to be at risk. In this work, several combinational circuits are selected and simulated, taking into account gate library and layout information, in order to characterize the effects of particle strikes which upset single nodes as well as multiple, physically adjacent nodes. It is shown that traditional reliability tests which simulate a single fault are not sufficient – multiple faults stemming from a single strike occur and are more complex. However, multiple faults do not always translate to additional errors in the output – logical reconvergence limits the effect of faults within a circuit. In order to properly understand reliability in circuit design, analysis of multiple faults should be taken into account.