dc.creator | Chatterjee, Indranil | |
dc.date.accessioned | 2020-08-21T21:33:49Z | |
dc.date.available | 2012-04-05 | |
dc.date.issued | 2012-04-05 | |
dc.identifier.uri | https://etd.library.vanderbilt.edu/etd-03252012-195135 | |
dc.identifier.uri | http://hdl.handle.net/1803/11296 | |
dc.description.abstract | CMOS technologies can be either dual-well or triple-well. Triple-well technology has several advantages compared to dual-well technology in terms of electrical performance. Differences in the ion-induced single-event response between these two technology options, however, are not well understood. This work presents a comparative analysis of heavy ion-induced upsets in dual-well and triple-well 40-nm CMOS SRAMs. Primary factors affecting the charge-collection mechanisms for a wide range of particle energies are investigated, showing that triple-well technologies are more vulnerable to low-LET particles, while dual-well technologies are more vulnerable to high-LET particles. For the triple-well technology, charge confinement and multiple-transistor charge collection triggers the “Single Event Upset Reversal” mechanism that reduces sensitivity at high LETs. | |
dc.format.mimetype | application/pdf | |
dc.subject | Soft-errors | |
dc.subject | Single-Event Upset Reversal | |
dc.subject | Heavy Ion Irradiation | |
dc.subject | Triple-well | |
dc.subject | Dual-well | |
dc.subject | Single-Event Effects | |
dc.title | Single-event charge collection and upset in 65-nm and 40-nm dual- and triple-well bulk CMOS SRAMS | |
dc.type | thesis | |
dc.contributor.committeeMember | Ronald D. Schrimpf | |
dc.type.material | text | |
thesis.degree.name | MS | |
thesis.degree.level | thesis | |
thesis.degree.discipline | Electrical Engineering | |
thesis.degree.grantor | Vanderbilt University | |
local.embargo.terms | 2012-04-05 | |
local.embargo.lift | 2012-04-05 | |
dc.contributor.committeeChair | Bharat L. Bhuva | |