Characterization of Single-Event Effects in Combinational Logic Using the C-CREST Technique

Abstract

As technology nodes scale smaller, digital circuits are able to run at higher clock frequencies, but they can become more susceptible to single-event induced errors. These types of errors can be generated in combinational logic and in storage cells. Traditional methods of characterizing digital circuits for single-event effects have difficulty distinguishing combinational logic errors from storage cell errors at high speeds.

In this thesis, a new approach of characterizing single-event effects in combinational logic is described called the Combinational Circuit for Radiation Effects Self-Test (C-CREST). This approach allows the SET cross-section of combinational logic to be increased while minimizing propagation delay. Various types of digital circuits can then be tested at speeds determined by their technology node along with allowing combinational logic errors to be distinguished from storage cell errors.