Evaluation of Fin Geometry and VT-Variant on Single-Event Effects in 7nm, 5nm, and 3nm Bulk FinFET Technologies

Abstract

Technology Computer-Aided Design (TCAD) simulations are used to clarify the underlying mechanisms affecting single-event upset results at 7nm, 5nm and 3nm bulk FinFET technologies using hard-biased, inverter, and latch configurations. The parameters varied for irradiation tests and simulations are threshold voltage (VT) and fin geometry. Results show that estimated changes in geometry and process parameters across these technology generations have minimal effects on collected charge, whereas circuit-level parameters strongly influence collected charge, single-event transient (SET) pulse widths, and, subsequently, single-event upset (SEU) cross-sections.