Novel and Evolving Single-Event Upset Vulnerability Factors in Advanced FinFET Technologies

Abstract

Single-event upsets (SEUs) can lead to data corruption and failures in electronic computing systems. As transistor structures and characteristics evolve with fabrication development, memory cell vulnerability to SEUs is constantly changing. In this work, static random-access memory (SRAM) cells in advanced bulk fin field-effect transistor (FinFET) technology nodes are characterized with different cell designs, operating parameters, and incident particle types. Technology computer-aided design (TCAD) tools are utilized to inform models and clarify underlying mechanisms. SEU characterizations across different supply voltages, incident particle linear-energy transfer (LET) values, and operating temperatures show significant changes in charge collection and circuit response across operating conditions. Characterizations of different SRAM cell designs show the effect of design decisions on SEU vulnerability. Increasing the number of transistor fins connected to a storage node results in significantly elevated SEU vulnerability and increased MCU sizes to high LET particles due to multiple-fin diffusion charge collection in dual-port SRAM cells. SRAM cells with asymmetry in parasitic capacitances exhibit preferred states and different single-event transient pulse characteristics depending on the storage state and the struck node. The combination of these factors leads to asymmetric storage cells showing significantly greater vulnerability in one storage state over the other. These results show the increasing importance of operating parameters and storage cell design decisions affecting SEU vulnerability in FinFET technologies, as well as the importance of thorough test campaigns to accommodate for worst-case conditions to accurately capture response.