Logic repair and soft error rate reduction using approximate logic functions

Abstract

Continuing CMOS devices scaling causes an increase in the vulnerability of integrated circuits to radiation-induced soft errors. Furthermore, as transistor density increases, the probability of transistors failing increases accordingly. Consequently, design approaches that address these threats to architectural reliability are required. Existing techniques for providing hardware robustness often require incurring significant area, power, speed, and weight penalties. Moreover, many of the existing techniques are only applicable to memory elements. In this project, a new technique for soft error rate reduction and logic repair using approximate logic functions has been developed. By utilizing this technique, designers can flexibly select the protection level of logic circuits while balancing out design trade-offs