Optimized Back-Biasing Strategy to Improve TID Tolerance in Conventional-Well 22nm FDSOI Transistors

Abstract

In a 22nm FDSOI CMOS technology architecture, back-biasing for total-ionizing-dose (TID) effects mitigation accelerates transistor degradation by increasing the rate of buried oxide (BOX) trapped charge accumulation. Conventional dynamic back-biasing maintains a constant threshold voltage shift (ΔVth) by continuously increasing the magnitude of back-gate voltages as total dose increases, unintentionally accelerating BOX charge accumulation. An optimized strategy instead delays compensatory back-biasing until the threshold voltage approaches its operational limit, minimizing early charge accumulation and reducing long-term degradation. Experimental results across various device sizes demonstrate that this approach lowers TID-induced threshold voltage shifts at larger doses. For example, in an 80/32 nm NMOS device, the optimized method reduced pre-annealing and post-annealing ΔVth increases due to back-biasing to 2% and <1%, compared to 17% and 12% when conventional back-biasing is used. This strategy effectively mitigates TID-induced degradation, enhancing device reliability at higher radiation doses.