Qualitative Characterization of Single-event Transient and Latchup Trends in 180 nm CMOS Technology

Abstract

Single-event upsets and errors are of growing concern as technology scales toward smaller transistor sizes. While smaller transistors allow for greater on-chip integration, this comes with the penalties of reduced supply voltage overhead and low drive currents compared to larger technologies. These penalties provide added challenges when considering the use of state of the art technologies for space based and strategic analog / mixed-signal applications. Therefore, it may prove beneficial to consider the use of slightly older technologies that avoid these penalties for such applications.In this study, the general usability of the 180 nm technology in a space environment setting was explored through simulation with an emphasis on analog / mixed-signal applications. While a bit dated, limited published data exists on this technology’s response to single events. Therefore, simulations were performed across variations in supply voltage, LET, and transistor load to generally characterize the technology’s susceptibility to single-event transients and single-event latchup. General observed trends are reported for these phenomena along with the effects of commonly used mitigation techniques including highly doped buried layers, guard rings, and triple-well NMOS devices.