Single-Event Effects in Silicon Carbide Power Devices for Space Applications

Abstract

Silicon Carbide (SiC) power devices offer transformative advantages over traditional Silicon (Si) components for space-based systems. Their superior material properties, including a higher breakdown electric field and greater thermal conductivity, enable significant reductions in system size, weight, and power (SWaP). These benefits are critical for high-power applications on space missions. However, the harsh radiation environment of space poses a significant reliability challenge. Commercial SiC devices are known to be susceptible to single-event effects (SEEs), where a single energetic particle can cause permanent damage or catastrophic failure, hindering their widespread adoption. This dissertation provides a comprehensive experimental investigation into the three primary SEE failure modes in high-voltage SiC power MOSFETs and diodes: catastrophic single-event burnout (SEB), permanent degradation via single-event leakage current (SELC), and latent gate damage. Standard SEE test methodologies developed for Si are inappropriate for SiC, as they fail to account for the unique physics of wide-bandgap devices. A critical finding is that prior degradation from SELC at lower biases can mask the true catastrophic SEB threshold, leading to inaccurate reliability assessments. To address this, a novel multi-stage SEE test methodology was developed and validated. This method combines a rapid bias sweep characterization to estimate failure thresholds with a meticulous discrete test-to-failure screening. This novel approach accurately and efficiently determines the true onset of both SELC and SEB, which was essential for this work. This research presents the first analytical models for SELC thresholds across a wide range of SiC devices (1200 V to 10,000 V). A key finding is that the SELC threshold (VSELC) is governed by two distinct physical mechanisms depending on the ion’s linear energy transfer (LET) values. At low LET (<15 MeV-cm²/mg), VSELC is primarily dependent on the epitaxial thickness (LEPI), following a critical power model (VSELC ∝LEPI1/2). At high LET (>30 MeV-cm²/mg), the mechanism transitions: VSELC becomes independent of thickness and is instead dictated by the epitaxial doping (NEPI), fitting a pre-strike critical energy storage model (VSELC ∝NEPI-1/3). A critical energy for SELC (USELC,sat) of approximately 90 µJ/cm² is identified in this work. Furthermore, experiments confirm that ions must penetrate the entire epitaxial layer to cause failure and that degradation is highest at normal (0°) incidence, decreasing significantly at tilt angles greater than 15° due to reduced power density. Finally, this work identifies the mechanism for latent gate damage in MOSFETs. High-LET ions create a transient, localized, and extremely high electric field in the JFET region, which enables Fowler-Nordheim tunneling and subsequent gate rupture during post-irradiation stress tests. This research provides the foundational models and test strategies required to design, optimize, and qualify high-voltage SiC power systems for reliable operation in space.