Soft error aware physical synthesis

Abstract

To allow accurate analysis of Soft Errors by Electronic Design Automation (EDA) tools, analytical models were developed to estimate electrical characteristics of the single event. The Ambipolar-Diffusion-With-Cutoff (ADC) model was extended in this work to model charge sharing, thus allowing accurate charge estimation by EDA tools An Single Event Transient (SET) pulse width estimation methodology was developed to model the Standard Cells response to the soft error. Combining these models along with circuit masking probabilities, the circuit soft-error cross-section is estimated. These soft error models are then integrated into an automatic standard cell placement tool based on Quadratic Optimization. Results show the impact of Physical Synthesis electrical correction techniques, such as Buffering, Gate Cloning and Gate Sizing, to the circuit soft error cross-section. Furthermore, an algorithm to reduce the circuit soft error cross-section by optimizing the Tap Cell placement was also developed and demonstrated. Results from this thesis provide key insights to control the circuit soft error cross-section during the Physical Synthesis design flow for integrated circuits at the most advanced technology nodes.