Simulated temperature dependency of SEU sensitivity in a 0.5 μm CMOS SRAM

Abstract

Application of advanced technology in remote, extreme environments can reduce system power, reduce launch weight and improve the overall reliability of the space mission. The Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) has been shown to have high tolerances to total ionizing dose. Furthermore, SiGe BiCMOS, a process technology implementing both SiGe HBT and Complimentary Metal Oxide Semiconductors (CMOS), has been shown to have the necessary performance to operate at cold temperatures. These features of this technology are essential in order to work in the above extreme environments. However, further study is needed to understand how BiCMOS reacts to Single Event Effects (SEE). The focus of this research is to study the CMOS portion of the BiCMOS process implemented as a Static Random Access Memory (SRAM) cell. By simulating an SRAM cell with Technology Computer Aided Design (TCAD) using a newly developed mixed-mode capability, this research shows that the digital CMOS SRAM cell has an increased sensitivity to Single Event Upsets (SEUs) at reduced temperatures driven by increased charge collection due to an increase in carrier mobilities. However, this increased sensitivity is still below the thresholds required to cause problems for the error management system for the memory cell and therefore radiation hardening will not be required for the SRAM at the cell level.