Single-Event Upset Characterization of Flip-Flops Across Temperature and Supply Voltage for a 20-nm Bulk, Planar, CMOS Technology

Abstract

The scaling of CMOS technology has brought about the increased susceptibility of circuits to single-event (SE) effects. Electronic systems operating in space often face extreme temperature conditions and high levels of radioactivity. Additionally, power management for space systems may require electronic circuits to operate at a lower than nominal supply voltage. Lowering the supply voltage results in decreased critical charge for storage cells, ultimately increasing SE failure rates. The combined effects of radiation, reduced voltage, and temperature may reduce the operating margin for circuit-level parameters, causing unexpected failures. This warrants further investigation into the SE effects of over a range of temperatures and reduced bias.Previous studies investigating the relationship between temperature and single-event transient (SET) pulse width have concluded that the SE response is dominated by parasitic bipolar effects. However, these bipolar effects are only triggered by high linear energy transfer (LET) particles which are relatively uncommon compared to the number of low LET particles typically encountered in space and terrestrial environments. In the absence of parasitic bipolar effects, other mechanisms such as modulation of carrier mobilities will dominate the SE response of circuits in high temperature environments. Therefore, this work addresses temperature effects on SE cross-sections for flip flops at the 20-nm technology node using low LET alpha particles. Experimental results indicate that cross-sections vary by up to 700% due to the temperature dependence of carrier mobilities. This trend holds true for a number of different flip flop designs with a range of radiation hardness.