Single Event Radiation Hardening of Sub-Sampling Phase-Locked Loops

Abstract

The phase-locked loop (PLL) is a fundamental building block of modern microelectronics. Due to its utility and adaptability this circuit serves countless functions throughout a wide range of systems. This work presents radiation-hardened by design techniques applied to a 15 GHz quadrature sub-sampling phase-locked loop at a sub-50nm partially depleted silicon-on-insulator technology node. Radiation hardening techniques are integrated in a sub-sampling architecture for robust noise and radiation performance. Experimentally validated bias dependent single event models are used to characterize the radiation response and the applicability of existing radiation-hardened by design techniques to sub-sampling phase-locked loops is examined. A significant vulnerability introduced in dual-loop PLL architectures such as sub-sampling is identified and mitigated with a proposed technique. Favorable noise and loop perturbation suppression characteristics of the sub-sampling architecture are leveraged to develop a high-performance radiation-hardened by design phase-locked loop maintaining performance specifications comparable to unhardened designs.