Single-Event Characterization of a 90-nm Bulk CMOS Digital Cell Library

Abstract

A single event occurs when an ionizing particle strikes a microelectronic circuit and deposits charge in the semiconductor material. Charge deposited by the particle is often collected by the circuit, resulting in a current transient that can lead to soft errors, depending on the circuit response. In this thesis, single-event (SE) mechanisms in combinational logic are discussed in the context of a 90-nm digital cell library in bulk CMOS. Technology Computer Aided Design (TCAD) simulations are used to investigate various parameters across different cell designs. Knowledge of the effects of layout- and circuit-level parameters on SE response is used to perform a TCAD characterization of a 90-nm digital cell library. The results give insight into the relative SE vulnerability of different types of logic cells.