Impact of process variations on soft error sensitivity of 32-nm VLSI circuits in near-threshold region
Power consumption has become a major concern of integrated circuit (IC) design. Reducing the supply voltage to the near-threshold region is one method to reduce the power consumption. However, operating in this region makes the circuit more sensitive to process variations. In the thesis, the impact of process variations on a 32-nm 6T SRAM cell and two kinds of flip-flops (transmission gate flip-flop and clocked CMOS flip-flop) under near-threshold voltage is studied. Monte Carlo method is used to evaluate the potential of the circuits for soft errors. The double exponential current source is used to simulate the strike of an ionizing particle. For the SRAM cell, the results show that threshold voltage variability is a more significant parameter affecting the critical charge distribution of the circuit under both the near-threshold voltage and the nominal supply voltage. For the flip-flops, the reduced supply voltage has little impact on the critical charge variation induced by process variations. Moreover, the near-threshold operation has much smaller leakage power than the nominal supply voltage. However, the delay time of the circuits is also greatly increased in near-threshold region.