Characterization of the mechanisms affecting single-event transients in sub-100 nm technologies

Abstract

As transistor density increases with each new CMOS technology node, the probability of a single ion causing a single-event transient in a circuit or inducing charge sharing among transistors increases. These transients can lead to single-event upsets that can cause a circuit or system to fail. Therefore, it is important to understand the characteristics of single-event transients at each new technology node and the resulting impacts on circuit designs. This dissertation uses both three-dimensional mixed-mode technology-computer-aided design simulations and experimental analysis at the 65 nm, 90 nm, and 130 nm technology nodes to fully characterize the mechanisms that affect single-event transients in sub-100 nm bulk CMOS technologies. Investigations show that the design parameter of n-well contact area influences the pulse width of single-event transients by controlling the degree of parasitic bipolar junction transistor amplification in pMOS transistors. Also the prevalence of charge sharing in sub-100 nm bulk CMO technologies has led to a new single-event mechanism called pulse quenching that can shorten or eliminate single-event transients. Furthermore, pulse quenching can lead to a new type of single-event transient called a double-pulse-single-event transient.