A clock-gated, double edge-triggered flip-flop implemented with transmission gates
Power is a critical issue in digital system design, especially with the emphasis on the portability of electronic devices. However, decreasing power does not necessarily lead to energy efficiency; designers need to consider the negative influence on performance when power is reduced. Trade-offs in circuit design should be evaluated using both power and performance. One important element of power consumption in a digital system is the flip-flop. This thesis surveys several previous designs of double edge-triggered flip-flops, and then proposes a transmission-gate-based, double edge-triggered flip-flop with a novel clock gating function. Two designs (with and without clock gating) are each compared against two benchmark circuit designs. Using the second benchmark circuit (from the literature), the Design II: P_DETFF with the clock gating function saved 33% power on average when the switching activity factor (α) ranged from 0 to 0.4. When the input is idle, it also can save up to 98% of the power compared to the baseline Benchmark I: SETFF. The Design I: T_DETFF showed better performance than any other designs when α was above 0.4. Comparing with the best benchmark in this range, it saved 23% of the power on average, and 27% when the input switches every clock cycle. The proposed designs required slightly more area than the benchmarks, but maintained performance across different frequencies.